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Freescale Semiconductor /MKE16F16 /SIM /CHIPCTL

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Interpret as CHIPCTL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0000)ADC_INTERLEAVE_EN 0 (00)CLKOUTDIV 0CLKOUTSEL 0 (0)TRACECLK_SEL 0 (0)PDB_BB_SEL 0 (0)CAN_FLT_CLK_SEL 0 (00)PWT_CLKSEL 0 (00)RTC_CLKSEL

PDB_BB_SEL=0, CAN_FLT_CLK_SEL=0, CLKOUTDIV=00, ADC_INTERLEAVE_EN=0000, TRACECLK_SEL=0, PWT_CLKSEL=00, RTC_CLKSEL=00

Description

Chip Control register

Fields

ADC_INTERLEAVE_EN

ADC interleave channel enable

0 (0000): No interleave channel
CLKOUTDIV

CLKOUT divider

0 (00): no divider

1 (01): div 2

2 (10): div 4
CLKOUTSEL

CLKOUT Select

1 (01): SCGCLKOUT(SIRC/FIRC/SOSC/LPFLL)

2 (10): RTC oscillator (OSC32) clock (32 kHz)
TRACECLK_SEL

Debug trace clock select

0 (0): core clock

1 (1): platform clock
PDB_BB_SEL

PDB back-to-back select

0 (0): PDB0 channel 0 back-to-back operation with ADC0 COCO[7:0]; PDB1 channel 0 back-to-back operation with ADC1 COCO[7:0] ; PDB2 channel 0 back-to-back operation with ADC2 COCO[7:0].

1 (1): Channel 0 of PDB0, PDB1 and PDB2 back-to-back operation with COCO[7:0] of ADC0, ADC1 and ADC2.
CAN_FLT_CLK_SEL

CAN filter clock select

0 (0): LPO clock

1 (1): SIRC clock
PWT_CLKSEL

PWT clock select

0 (00): TCLK0

1 (01): TCLK1

2 (10): TCLK2
RTC_CLKSEL

RTC clock select

0 (00): OSC32_CLK

1 (01): RTC_CLKIN

2 (10): SOSC_CLK

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data